1. Field of the Invention
The present invention relates to an image decoding unit, image encoding/decoding devices using the image decoding unit, and a method thereof. In particular, it relates to an art of high-speed processing in generating reconstructed images.
2. Description of the Related Art
In recent years, as information devices and information terminals which can treat moving pictures have rapidly progressed, technology to compress the moving pictures has attracted increasing attention.
The moving picture compression technology has been standardized by standards such as MPEG-2 and MPEG-4 proposed by MPEG (Moving Picture Experts Group), or H.261, H.263 and H.264 proposed by ITU (International Telecommunication Union). The moving picture compression technology according to these standards compresses moving pictures in extreme compactness, utilizing a strong correlation between a frame and its adjacent frame in the moving pictures.
First of all, a general prior art on moving picture compression will be explained, with reference to FIGS. 10 to 12.
FIG. 10 shows a block diagram illustrating an image encoding device in the prior art. Construction and operation of the image encoding device is roughly explained in the following.
The image encoding device in the prior art shown in FIG. 10 is a general image encoding device. The image encoding device comprises an input terminal 10, subtractor 11, a DCT unit (a discrete cosine transformer) 12, a quantizer 13, an entropy encoder 14, a sending buffer 15, an output terminal 16, a motion detector 17, an inverse quantizer 19, an inverse DCT unit 21, a motion compensator 22, an adder 23 and a frame memory 24.
The input terminal 10 connects with one of inputs of the subtractor 11 and one of inputs of the motion detector 17. Another input of the subtractor 11 connects with an output of the motion compensator 22. Another input of the motion detector 17 connects with an output of the frame memory 24.
An output of the subtractor 11 connects with an input of the DCT unit 12. An output of the DCT unit 12 connects with an input of the quantizer 13. An output of the quantizer 13 connects with an input of the entropy encoder 14 and an input of the inverse quantizer 19. Another input of the entropy encoder 14 connects with an output of the motion detector 17. An output of the entropy encoder 14 connects with an input of the sending buffer 15.
An output of the inverse quantizer 19 connects with an input of the inverse DCT unit 21. An output of the inverse DCT unit 21 connects with one of inputs of the adder 23. Another input of the adder 23 connects with an output of the motion compensator 22. An output of the adder 23 connects with the frame memory 24. The frame memory 24 also connects with another input of the motion detector 17.
Now, the operation of the image encoding device is outlined. An input image signal S10 at the input terminal 10 is fed to the motion detector 17. The motion detector 17 compares the input image signal S10 with a reconstructed image (often called as a reference image) which is stored in the frame memory 24, to generate a motion vector S11. Using the motion vector S11, the motion compensator 22 generates a prediction image S12. The subtractor 11 calculates a difference between the input image signal S10 and the prediction image S12, the difference being a prediction error. The prediction error is fed to the DCT unit 12 to generate DCT coefficients. The DCT coefficients is fed to and quantized by the quantizer 13. The quantized DCT coefficients are encoded by the entropy encoder 14, together with the motion vector S11, into a variable length code such as a Huffman code or an arithmetic code. The variable length code is temporarily stored in the sending buffer 15 and sent out in a bit stream.
The quantized DCT coefficients are also processed by the inverse quantizer 19 and the inverse DCT unit 21, thus generating a local prediction error data S14. Using the local prediction error data S14 and the prediction image S12 generated by the motion compensator 22, the adder 23 generates a reconstructed image and stores the reconstructed image into the frame memory 24.
In a motion vector detection process, the motion detector 17 treats, as a process target block, a block made of several pixels within the present image. Utilizing a so-called block matching method, the motion detector 17 searches a location of the process target block in an image time-wisely previous to the present image, and detects a motion vector that indicates the direction and amount of the movement of the present image.
The motion compensator 22 adopts a method which makes the prediction error smaller by generating the prediction image S21 not only in a unit of a pixel but also in a unit of a subdivided pixel. The generation of a prediction image in a unit of a pixel is called full-pel motion compensation. On the contrary, the generation of a prediction image in a unit of a subdivided pixel is called sub-pel motion compensation, more specifically, it is called half-pel motion compensation when the subdivision is a half of a pixel, and quarter-pel motion compensation when the subdivision is a quarter of a pixel.
FIG. 11 shows a block diagram illustrating an image decoding device in the prior art. Referring to FIG. 11, a general decoding method is explained in the following.
The image decoding device in the prior art shown in FIG. 11 is a general image decoding device. The image decoding device comprises an input terminal 30, a receiving buffer 31, an entropy decoder 32, an inverse quantizer 19, an inverse DCT unit 21, a motion compensator 22, an adder 23, a frame memory 24, and an output terminal 33.
The input terminal 30 connects with an input of the receiving buffer 31. An output of the receiving buffer 31 connects with an input of the entropy decoder 32. An output of the entropy decoder 32 connects with an input of the inverse quantizer 19 and one of inputs of the motion compensator 22
An output of the inverse quantizer 19 connects with an input of the inverse DCT unit 21. An output of the inverse DCT unit 21 connects with one of inputs of the adder 23. Another input of the motion compensator 22 connects with an output of the frame memory 24. Another input of the adder 23 connects with output of the motion compensator 22. An output of the adder 23 connects with an input of the frame memory 24. An output of the frame memory 24 connects with the output terminal 33.
Now, the operation of the image decoding device is outlined. A received bit stream at the input terminal 30 is temporarily stored in the receiving buffer 31 and then fed to the entropy decoder 32.
The entropy decoder 32 decodes from the received bit stream a motion vector S31 and quantized DCT coefficients S32 for a prediction error. The quantized DCT coefficients S32 is processed by the inverse quantizer 19 and the inverse DCT unit 21, to generate DCT coefficients S35 for the prediction error. Then the DCT coefficients S35 is fed to the adder 23.
Meanwhile, the motion vector decoded by the entropy decoder 32 is fed to the motion compensator 22. The motion compensator 22 compensates a motion for a reconstructed image S33 stored in the frame memory 24, to generate a prediction image S34, which is subsequently fed to the adder 23. Adding the prediction image S34 and the DCT coefficients S35, the adder 23 generates a new reconstructed image S36 and stores it into the frame memory 24. The newly generated reconstructed image is provided from the frame memory 24 to the output terminal as a decoded image S37, then, displayed on an image display device externally installed.
In the motion compensation processed by the motion compensator 22, sub-pel motion compensation is sometime made, in addition to full-pel motion compensation, as in the image encoding device described above.
The area 20 surrounded by dot-and-dash lines shown in FIG. 10 is completely same, in terms of construction and functions of each elements included, as the counterpart area 20 shown in FIG. 11. (For this reason, the same numbers are labeled to the same elements in both figures.)
It should be noticed that the construction of the area 20 can be equally utilized in the image encoding device and the image decoding device.
A patent reference no. 1 (PCT international patent publication no. WO-9502948) disclosed a further device for the area 20 concerned.
FIG. 12 shows a block diagram illustrating a motion compensator to be used in a conventional moving image decoder, corresponding to FIG. 10 of the patent reference no.1. In FIG. 12, the same names as in but different numerical labels from the patent reference no.1 are used.
As shown in FIG. 12, a motion compensator 40 to be used in the conventional moving image decoder comprises an IDCT (Inverse Discrete Cosine Transformer) 41, which is the same as the Inverse DCT unit shown in FIG. 10, an MB (Macro Block) buffer 42, an adder 43, which is the same as the adder 23 in FIG. 10, a DRAM writing buffer 44 and a reference frame memory 45, which is the same as the frame memory 24 in FIG. 10. The MB buffer 42 comprises two banks, and the DRAM writing buffer 44 comprises a bank. The reference frame memory may be made of DRAMs.
The principal feature of the device shown in FIG. 12 lies in absorbing a difference in speed between reading from the IDCT 41 and writing into the reference frame memory 45, by providing the MB buffer 42, and in adjusting timing in reading and writing in the reference frame memory 45, by providing the DRAM writing buffer 44.
More specifically, the adder 43 adds a prediction macro block signal S44 fed by the reference frame memory 45 and an output signal S42 of the MB buffer 42, and generates a reconstructed image signal S43, which is subsequently written into the DRAM writing buffer 44. The DRAM writing buffer 44 retains the reconstructed image signal S43 until the reference frame memory 45 becomes ready for writing. The DRAM writing buffer 44 writes the reconstructed image signal S43 into the reference frame memory 45 when the reference frame memory 45 becomes ready. By the scheme described above, the inventors of the patent reference no. 1 claim that a low-speed, cost-saving DRAM can be used for the reference frame memory 45.
When the reference frame memory 45 possesses reading and writing speeds faster than a reading speed of the IDCT 41, by providing the DRAM writing buffer 44 with a bank, the bank is always empty when block data is inputted, since the block data inputted into the bank is read out before the next block data is inputted. By this device, the inventors of the patent reference no.1 further claim that memory size necessary for the timing adjusting buffer can be made smaller, thus reducing a scale of the hardware.
However, the device shown in FIG. 12 is just for full-pel motion compensation and can not treat sub-pel motion compensation.
As is made clear by the above description, the prior arts can not perform, with high efficiency and high-speed, the sub-pel motion compensation that is required for the recent image standards.